Team Alex Bradbury At Igalia since March 2022. Cambridge (UK) Follow me asb (at) igalia.com muxup.com fosstodon.org/@asb twitter.com/asbradbury github.com/asb linkedin.com/in/alex-bradbury POSTS Apr 10, 2023 Updating Wren's benchmarks Wren is a “small, fast, class-based, concurrent scripting language”, originally designed by Bob Nystrom (who you might recognise as the author of Game Programming Patterns and Crafting Interpreters. It’s a... Continue reading > Apr 10, 2023 2023Q2 week log I tend to keep quite a lot of notes on the development related (sometimes at work, sometimes not) I do on a week-by-week basis, and thought it might be fun... Continue reading > Mar 18, 2023 What's new for RISC-V in LLVM 16 LLVM 16.0.0 was just released today, and as I did for LLVM 15, I wanted to highlight some of the RISC-V specific changes and improvements. This is very much a... Continue reading > Mar 3, 2023 Commercially available RISC-V silicon The RISC-V instruction set architecture has seen huge excitement and growth in recent years (10B cores estimated to have shipped as of Dec 2022) and I’ve been keeping very busy... Continue reading > Tweets Jun 2, 2023 Join me at #RISCVSummiteurope next week in Barcelona where I’ll be delivering an invited keynote “Developments in LLVM-based toolchains and... Jun 2, 2023 Join me at #RISCVSummiteurope next week in Barcelona where I’ll be delivering an invited keynote “Developments in LLVM-based toolchains and... May 19, 2023 There’s a number of RISC-V mentions in the just-published UK National Semiconductor strategy. https://gov.uk/government/publications/national-semiconductor-strategy/national-semiconductor-strategy including this “next step” May 19, 2023 There’s quite a few RISC-V mentions in the just-published UK National Semiconductor strategy. https://t.co/oEGOhvAMZ7 including this “next step” https://t.co/FlnjC0YhSd Commits May 30, 2023 [LLVM] [RISCV] Generalise shouldExtendTypeInLibcall logic to apply to all May 29, 2023 [LLVM] [RISCV][test] Expand bfloat.ll tests to include i16 bitcasts and load… May 29, 2023 [LLVM] [SelectionDAG] Implement soft FP legalisation for bf16 FP_EXTEND and … May 23, 2023 [LLVM] [RISCV] Make zfbfmin imply the F extension
Apr 10, 2023 Updating Wren's benchmarks Wren is a “small, fast, class-based, concurrent scripting language”, originally designed by Bob Nystrom (who you might recognise as the author of Game Programming Patterns and Crafting Interpreters. It’s a... Continue reading >
Apr 10, 2023 2023Q2 week log I tend to keep quite a lot of notes on the development related (sometimes at work, sometimes not) I do on a week-by-week basis, and thought it might be fun... Continue reading >
Mar 18, 2023 What's new for RISC-V in LLVM 16 LLVM 16.0.0 was just released today, and as I did for LLVM 15, I wanted to highlight some of the RISC-V specific changes and improvements. This is very much a... Continue reading >
Mar 3, 2023 Commercially available RISC-V silicon The RISC-V instruction set architecture has seen huge excitement and growth in recent years (10B cores estimated to have shipped as of Dec 2022) and I’ve been keeping very busy... Continue reading >
Jun 2, 2023 Join me at #RISCVSummiteurope next week in Barcelona where I’ll be delivering an invited keynote “Developments in LLVM-based toolchains and...
Jun 2, 2023 Join me at #RISCVSummiteurope next week in Barcelona where I’ll be delivering an invited keynote “Developments in LLVM-based toolchains and...
May 19, 2023 There’s a number of RISC-V mentions in the just-published UK National Semiconductor strategy. https://gov.uk/government/publications/national-semiconductor-strategy/national-semiconductor-strategy including this “next step”
May 19, 2023 There’s quite a few RISC-V mentions in the just-published UK National Semiconductor strategy. https://t.co/oEGOhvAMZ7 including this “next step” https://t.co/FlnjC0YhSd