Team Alex Bradbury At Igalia since March 2022. Cambridge (UK) Follow me muxup.com fosstodon.org/@asb twitter.com/asbradbury github.com/asb linkedin.com/in/alex-bradbury POSTS Feb 20, 2024 Clarifying instruction semantics with P-Code I’ve recently had a need to step through quite a bit of disassembly for different architectures, and although some architectures have well-written ISA manuals it can be a bit jarring... Continue reading > Jan 1, 2024 Reflections on ten years of LLVM Weekly Today, with Issue #522 I’m marking ten years of authoring LLVM Weekly, a newsletter summarising developments on projects under the LLVM umbrella (LLVM, Clang, MLIR, Flang, libcxx, compiler-rt, lld, LLDB,... Continue reading > Dec 24, 2023 Let the (terminal) bells ring out I just wanted to take a few minutes to argue that the venerable terminal bell is a helpful and perhaps overlooked tool for anyone who does a lot of their... Continue reading > Dec 20, 2023 Ownership you can count on Introduction I came across the paper Ownership You Can Count On (by Adam Dingle and David F. Bacon, seemingly written in 2007) some years ago and it stuck with me... Continue reading > Tweets May 2, 2024 RISC-V vector unit configurations: gotta catch ‘em allhttps://github.com/chipsalliance/t1#build May 1, 2024 Slides and video from the ‘CHERITech’ workshop are now available. Well worth a look through. https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/workshops/2024cheritech/Can anyone help decode this... Apr 29, 2024 So how many components are in a normalised target triple?You said four right? Well of course! And apparently Clang has... Apr 24, 2024 I’m surprised this initial support for SWAR vectorisation in LLVM didn’t need more code https://github.com/llvm/llvm-project/pull/69306/filesOf course I also know all... Commits Apr 26, 2024 [LLVM] [RISCV][NFC] Future-proof reference to ISA manual in RISCVInstrInfoC.td Apr 26, 2024 [LLVM] Revert "[RISCV] Support RISCV Atomics ABI attributes (#84597)" Apr 26, 2024 [LLVM] Revert "[llvm][RISCV] Enable trailing fences for seq-cst stores by de… Apr 25, 2024 [LLVM] [CodeGenPrepare] Preserve flags (such as nsw/nuw) in SinkCast (#89904)
Feb 20, 2024 Clarifying instruction semantics with P-Code I’ve recently had a need to step through quite a bit of disassembly for different architectures, and although some architectures have well-written ISA manuals it can be a bit jarring... Continue reading >
Jan 1, 2024 Reflections on ten years of LLVM Weekly Today, with Issue #522 I’m marking ten years of authoring LLVM Weekly, a newsletter summarising developments on projects under the LLVM umbrella (LLVM, Clang, MLIR, Flang, libcxx, compiler-rt, lld, LLDB,... Continue reading >
Dec 24, 2023 Let the (terminal) bells ring out I just wanted to take a few minutes to argue that the venerable terminal bell is a helpful and perhaps overlooked tool for anyone who does a lot of their... Continue reading >
Dec 20, 2023 Ownership you can count on Introduction I came across the paper Ownership You Can Count On (by Adam Dingle and David F. Bacon, seemingly written in 2007) some years ago and it stuck with me... Continue reading >
May 2, 2024 RISC-V vector unit configurations: gotta catch ‘em allhttps://github.com/chipsalliance/t1#build
May 1, 2024 Slides and video from the ‘CHERITech’ workshop are now available. Well worth a look through. https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/workshops/2024cheritech/Can anyone help decode this...
Apr 29, 2024 So how many components are in a normalised target triple?You said four right? Well of course! And apparently Clang has...
Apr 24, 2024 I’m surprised this initial support for SWAR vectorisation in LLVM didn’t need more code https://github.com/llvm/llvm-project/pull/69306/filesOf course I also know all...